library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity SwitchFabric is
  port( 							
    clk, reset: in std_logic;
	--inputs from rcv to SF_rcv_interface
	rcv0_data, 	rcv1_data, 	rcv2_data, 	rcv3_data: in std_logic_vector(7 downto 0);
	rcv0_length,rcv1_length,rcv2_length,rcv3_length: in std_logic_vector(11 downto 0);
	rcv0_qempty,rcv1_qempty,rcv2_qempty,rcv3_qempty: in std_logic;
	
	--outputs to rcv from SF_rcv_interface
	rcv0_drdreq, 	rcv1_drdreq, 	rcv2_drdreq, 	rcv3_drdreq: out std_logic;
	rcv0_lrdreq, 	rcv1_lrdreq, 	rcv2_lrdreq, 	rcv3_lrdreq: out std_logic;
	

	
	--inputs from table to SF_table_interface
	TSF_DS_PortNum : in STD_LOGIC_VECTOR (1 downto 0);
	TSF_OutputP_ready,	TSF_Bcast: in STD_LOGIC;
	 
	
	--outputs to table from SF_table_interface
	SFT_req_out: Out STD_LOGIC;
	SFT_RDone: Out STD_LOGIC;
	SFT_SportN: Out STD_LOGIC_VECTOR(1 downto 0);
	SFT_DMac_add_out, SFT_SMac_add_out : Out STD_LOGIC_VECTOR(7 downto 0);
		
	
	
	--inputs from xmt to SF_fifo2xmt_interface
	xmt0_wused,	xmt1_wused,	xmt2_wused,	xmt3_wused: in std_logic_vector(12 downto 0);

	--outputs to xmt from SF_fifo2xmt_interface
	xmt_all_data: out std_logic_vector (7 downto 0);     -- out to xmt D FIFOs
	xmt_all_length: out std_logic_vector (11 downto 0);    -- out to xmt L FIFOs
	xmt_dwreq, xmt_lwreq: out std_logic_vector (3 downto 0) --read/write request to xmt data and length FIFOs	
  );  
end SwitchFabric;

Architecture arch of SwitchFabric is 

------------Signals

--	--outputs from rcv_interface to RecHandle
--	signal rcv_port_number_from_rcv: std_logic_vector(1 downto 0);
--	signal rcv_connection_ready: std_logic;
--	signal rcv_data: std_logic_vector(7 downto 0);
--	signal rcv_length: std_logic_vector(11 downto 0);
--	
--	--inputs from RecHandle to rcv_interface
--	signal rcv_drdreq, rcv_lrdreq, packet_finished: std_logic;

	--outputs from RecHandle to SF_table_interface
    Signal rcv_port_number_to_xmt: std_logic_vector(1 downto 0);
	
	--inputs from SF_table_interface to RecHandle
	--there are none
	

	--Internal FIFO Signals

	--output port number FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
	signal pfifo_wreq, pfifo_full: std_logic; --pfifo will never be full (pfifo_full)
	signal pfifo_input: std_logic_vector(3 downto 0);  --changed from 3 to 4 bits
	
	--address FIFO signals
	signal afifo_rdreq, afifo_wreq, afifo_empty, afifo_full: std_logic;
	signal afifo_input, afifo_output: std_logic_vector(7 downto 0);
	
	--length FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
	signal lfifo_wreq, lfifo_full: std_logic;
	signal lfifo_input: std_logic_vector(11 downto 0);

	--data FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
	signal dfifo_wreq, dfifo_full: std_logic;
	signal dfifo_input: std_logic_vector(7 downto 0);
	

------------Components
	component SF_receive_side is
	port(
		clk, reset: in std_logic;
		--inputs from rcv to SF_rcv_interface
		rcv0_data, 	rcv1_data, 	rcv2_data, 	rcv3_data: in std_logic_vector(7 downto 0);
		rcv0_length,rcv1_length,rcv2_length,rcv3_length: in std_logic_vector(11 downto 0);
		rcv0_qempty,rcv1_qempty,rcv2_qempty,rcv3_qempty: in std_logic;
	
		--outputs to rcv from SF_rcv_interface
		rcv0_drdreq, 	rcv1_drdreq, 	rcv2_drdreq, 	rcv3_drdreq: out std_logic;
		rcv0_lrdreq, 	rcv1_lrdreq, 	rcv2_lrdreq, 	rcv3_lrdreq: out std_logic;
	
		--inputs from SF_table_interface to RecHandle
		--there are none
	
		--outputs from RecHandle to SF_table_interface
		rcv_port_number_to_xmt: out std_logic_vector(1 downto 0);
		
		--address FIFO signals
		afifo_wreq:		out std_logic;
		afifo_empty: 	in std_logic;
		afifo_input:	out std_logic_vector(7 downto 0);
		
		--length FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
		lfifo_wreq:		out std_logic;
		lfifo_full: 	in std_logic;
		lfifo_input: 	out std_logic_vector(11 downto 0);
	
		--data FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
		dfifo_wreq:		out std_logic;
		dfifo_full: 	in std_logic;
		dfifo_input: 	out std_logic_vector(7 downto 0)
	);
	end component;


	component SF_ODLFifo_xmtInterface_Xmt0to3 is  --(jacob)
    port(
	    clk, reset: in std_logic;
		
		--length FIFO signals
		lfifo_wreq:  in std_logic;
		lfifo_full: out std_logic;
		lfifo_input: in std_logic_vector(11 downto 0);--, lfifo_output: std_logic_vector(11 downto 0);

		--data FIFO signals
		dfifo_wreq: in std_logic;
		dfifo_full: out std_logic;
		dfifo_input: in std_logic_vector(7 downto 0);
	
		--output port number FIFO signals
		pfifo_wreq: in std_logic; 
		pfifo_full: out std_logic;
		pfifo_input: in std_logic_vector(3 downto 0); -- changed from 3 to 4 bits

		--inputs from xmt to SF_fifo2xmt_interface
		xmt0_wused,	xmt1_wused,	xmt2_wused,	xmt3_wused: in std_logic_vector(12 downto 0);

		--outputs to xmt from SF_fifo2xmt_interface
		o_D_xmt: out std_logic_vector (7 downto 0);     -- out to xmt D FIFOs
		o_L_xmt: out std_logic_vector (11 downto 0);    -- out to xmt L FIFOs
		xmt_dwtreq, xmt_lwtreq: out std_logic_vector (3 downto 0) --write request to xmt data and length FIFOs	

    );
    end component;
 
 
    component SF_table_interface is
 		Port ( 
		reset:In STD_LOGIC;
		clk : In STD_LOGIC; 
       --data input port number from RecHandle 
        Rcv_SportN: In STD_LOGIC_VECTOR(1 downto 0);
       
       --address FIFO signals  		
        Add_Fifo_empty: In STD_LOGIC;
        Add_Fifo_data: In STD_LOGIC_VECTOR(7 downto 0);
        Add_Fifo_rdreq_out : out STD_LOGIC;
       
       --output port number FIFO signals for pfifo
              
		Outp_Fifo_Pdata : Out STD_LOGIC_VECTOR (3 downto 0);   -- change from 3 to 4bits
		OutP_Fifo_wreq_out : out STD_LOGIC;
	   --SF-table signals 
		
		TSF_DS_PortNum : In STD_LOGIC_VECTOR (1 downto 0);
		TSF_Bcast: in STD_LOGIC;
		TSF_OutputP_ready: In STD_LOGIC; 
		
		SFT_req_out: Out STD_LOGIC;
		SFT_SportN: Out STD_LOGIC_VECTOR(1 downto 0);
		
			
		SFT_SMac_add_out : Out STD_LOGIC_VECTOR(7 downto 0);
		SFT_DMac_add_out : Out STD_LOGIC_VECTOR(7 downto 0);

 				
		SFT_RDone: Out STD_LOGIC
		);
	End component;
	
		
	--Switch Fabric FIFO
	
	component Add_Fifo IS
	PORT(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		empty		: OUT STD_LOGIC ;
		full		: OUT STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
		);
	END component;
	

-- Instantiations


	begin
	receive_side: SF_receive_side PORT MAP(
		clk			=> clk,
		reset		=> reset,
		--inputs from rcv to SF_rcv_interface
		rcv0_data	=> rcv0_data,
		rcv1_data	=> rcv1_data,
		rcv2_data	=> rcv2_data,
		rcv3_data	=> rcv3_data,
		rcv0_length	=> rcv0_length,
		rcv1_length	=> rcv1_length,
		rcv2_length	=> rcv2_length,
		rcv3_length	=> rcv3_length,
		rcv0_qempty	=> rcv0_qempty,
		rcv1_qempty	=> rcv1_qempty,
		rcv2_qempty	=> rcv2_qempty,
		rcv3_qempty	=> rcv3_qempty,
	
		--outputs to rcv from SF_rcv_interface
		rcv0_drdreq	=> rcv0_drdreq,
		rcv1_drdreq	=> rcv1_drdreq,
		rcv2_drdreq	=> rcv2_drdreq,
		rcv3_drdreq	=> rcv3_drdreq,
		
		rcv0_lrdreq	=> rcv0_lrdreq,
		rcv1_lrdreq	=> rcv1_lrdreq,
		rcv2_lrdreq	=> rcv2_lrdreq,
		rcv3_lrdreq => rcv3_lrdreq,
	
		--outputs from RecHandle to SF_table_interface
		rcv_port_number_to_xmt	=> rcv_port_number_to_xmt,
		
		--address FIFO signals
		afifo_wreq	=> afifo_wreq,
		afifo_empty	=> afifo_empty,
		afifo_input	=> afifo_input,
		
		--length FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
		lfifo_wreq	=> lfifo_wreq,
		lfifo_full	=> lfifo_full, --: 	in std_logic;
		lfifo_input	=> lfifo_input, --: 	out std_logic_vector(11 downto 0);
	
		--data FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
		dfifo_wreq	=> dfifo_wreq, --:		out std_logic;
		dfifo_full	=> dfifo_full, --: 	in std_logic;
		dfifo_input	=> dfifo_input	 --: 	out std_logic_vector(7 downto 0)
		
	);
		
		
	fifo2xmt_interface : SF_ODLFifo_xmtInterface_Xmt0to3 PORT MAP( --(jacob)
	    clk 	=> clk,
	    reset	=> reset,
		
		--length FIFO signals
		lfifo_wreq	=> lfifo_wreq,	   	--in from Rcv side  (xuan)
		lfifo_full	=> lfifo_full,		-- don't know if Xuan gets this or not could be open
		lfifo_input	=> lfifo_input,	   	--in from Rcv side (xuan)

		--data FIFO signals
		dfifo_wreq	=> dfifo_wreq,		-- in from rcvr (xuan)
		dfifo_full	=> dfifo_full,		-- don't know if Xuan gets this or not could be open
		dfifo_input => dfifo_input, 	--in from rcvr (xuan)
	
		--output port number FIFO signals
		pfifo_wreq	=> pfifo_wreq,  	--input from SF table (wwz)
		pfifo_full	=> open,  			--monitor for SF table (wwz)
		pfifo_input	=> pfifo_input,  	--input from SF table (wwz)

		--inputs from xmt to SF_fifo2xmt_interface
		xmt0_wused	=> xmt0_wused,
		xmt1_wused	=> xmt1_wused,
		xmt2_wused	=> xmt2_wused,
		xmt3_wused	=> xmt3_wused,

		--outputs to xmt from SF_fifo2xmt_interface
		o_D_xmt		=> xmt_all_data, 	-- out to xmt D FIFOs
		o_L_xmt		=> xmt_all_length,	-- out to xmt L FIFOs
		xmt_dwtreq	=> xmt_dwreq,
		xmt_lwtreq	=> xmt_lwreq		--read/write request to xmt data and length FIFOs	
    );



	TSF_interface: SF_table_interface PORT MAP
    ( 
		reset				=>	reset,
		clk	            	=>	clk,  
       --data input port number
        Rcv_SportN			=>	rcv_port_number_to_xmt,
        Add_Fifo_empty		=>	afifo_empty,
        Add_Fifo_data   	=>	afifo_output, --changed to afifo_output (BEF 3-28-09)
        Add_Fifo_rdreq_out	=> 	afifo_rdreq,
       
       --output port number FIFO signals for pfifo

		Outp_Fifo_Pdata 	=>	pfifo_input,
		OutP_Fifo_wreq_out	=>	pfifo_wreq, 
	   --SF-table signals 
		
		TSF_DS_PortNum		=>	TSF_DS_PortNum,
		TSF_Bcast			=>	TSF_Bcast,
		TSF_OutputP_ready	=>	TSF_OutputP_ready, 
		
		SFT_req_out			=>	SFT_req_out,
		SFT_SportN			=>	SFT_SportN,
		
			
		SFT_SMac_add_out	=>	SFT_SMac_add_out,
		SFT_DMac_add_out	=>	SFT_DMac_add_out,
		
		SFT_RDone			=>	SFT_RDone
	);

	--Switch Fabric Internal FIFOs	
    afifo: Add_Fifo Port MAP   ---MAC address fifo shared by Xuan and Wz
	(
		aclr		=>	reset,
		clock		=>	clk,
		data		=>	afifo_input,		
		rdreq		=>	afifo_rdreq,		--SF_table_interface      
		wrreq		=>	afifo_wreq,
		empty		=>	afifo_empty,		--SF_table_interface 
		full		=>	open,
		q		    => 	afifo_output		--SF_table_interface 
	);


end arch;